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80608hkim 20070314-s00003 no.a0744-1/29 ver.1.03 lc875cc8a LC875CB2A overview the sanyo lc875cc8a/b2a are 8-bit microcomputer that, centered around a cpu runnin g at a minimum bus cycle time of 83.3ns, integrate on a single ch ip a number of hardware features such as 128k/112k-byte rom, 4k-byte ram, two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), four 8-bit tim ers with a prescaler, a base timer serving as a time-of-day clock, two synchronou s sio ports (with automatic block transmission/reception capabilities), an asynchronous/synchronous sio port, two uart ports (full duplex), four 12-bit pwm channels, an 8-bit 15-channel ad converter, a high-speed clock counter, a system clock frequency divider, and a 29-source 10-vector interrupt feature. features ? rom ? 131072 8 bits (lc875cc8a) ? 114688 8 bits (LC875CB2A) ? ram ? 4096 9 bits ? minimum bus cycle time ? 83.3ns (12mhz) note: bus cycle time indicates the speed to read rom. ? minimum instruction cycle time (tcyc) ? 250ns (12mhz) ordering number : ena0744 cmos ic rom 128k/112k byte, ram 4096 byte on-chip 8-bit 1-chip microcontroller specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
lc875cc8a/b2a no.a0744-2/29 ? ports ? normal withstand voltage i/o ports ports whose i/o direction can be designated in 1 bit units: 64 (p1n, p2n, p3n, p70 to p73, p8n, pan, pbn, pcn, s2pn, pwm0, pwm1, xt2) ports whose i/o direction can be designated in 2 bit units: 16 (pen, pfn) ports whose i/o direction can be designated in 4 bit units: 8 (p0n) ? normal withstand voltage input ports: 1 (xt1) ? dedicated oscillator ports: 2 (cf1, cf2) ? reset pin: 1 ( res ) ? power pins: 8 (v ss 1 to v ss 4, v dd 1 to v dd 4) ? timers - timer 0: 16-bit timer/counter with capture registers mode 0: 8-bit timer with an 8-bit programmable prescal er (with two 8-bit capture registers) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) mode 3: 16-bit counter (with 2 16-bit capture registers) - timer 1: 16-bit timer/counter that support pwm/ toggle outputs mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also from the lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used as pwm.) - timer 4: 8-bit timer with a 6-bit prescaler - timer 5: 8-bit timer with a 6-bit prescaler - timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) - timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) - base timer 1) the clock is selectable from the subclock (32.768 khz crystal oscillator), system clock, and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes. ? high-speed clock counter 1) can count clocks with a maximum clock rate of 20mhz (at a main clock of 10mhz). 2) can generate output real time. ? sio ? sio 0: 8 bit synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tcyc) 3) automatic continuous data transmission (1 to 256 bits) ? sio 1: 8 bit asynchronous/s ynchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? sio2: 8 bit synchronous serial interface 1) lsb first mode 2) built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tcyc) 3) automatic continuous data transmission (1 to 32 bytes) ? uart: 2 channels 1) full duplex 2) 7/8/9 bit data bits selectable 3) 1 stop bit (2 bits in continuous transmission mode) 4) built-in baudrate generator (with baudrates of 16/3 to 8192/3 tcyc)
lc875cc8a/b2a no.a0744-3/29 ? ad converter: 8 bits 15 channels ? analog reference voltage can selected from v dd 1 or v dd 3. ? pwm: multifrequency 12-bit pwm 4 channels ? remote control receiver circuit (sharing pins with p73, int3, and t0in) 1) noise filtering function (noise filter time constant selectable from 1 tcyc, 32 tcyc, and 128 tcyc) 2) the noise filtering function is available for the int3, t0in, or t0hcp signal at p73. when p73 is read with an instruction, the signal level at that pin is read regardless of the availability of the noise filtering function. ? watchdog timer 1) external rc watchdog timer 2) interrupt and reset signals selectable ? interrupts ? 29 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector selectable level interrupt signal 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h/int6 6 0002bh h or l t1l/t1h/int7 7 00033h h or l sio0/uart1 receive/uart2 receive 8 0003bh h or l sio1/sio2/uart 1 transmit/uart2 transmit 9 00043h h or l adc/t6/t7/pwm4, pwm5 10 0004bh h or l port 0/t4/t5/pwm0, pwm1 ? priority level: x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 2048 levels maximum (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? rc oscillator circuit (internal): for system clock ? cf oscillator circuit: for system clock with internal rf ? crystal oscillator circuit: for low-speed system clock ? multifrequency rc oscillator circuit (internal): for system clock ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (at a main clock rate of 10mhz).
lc875cc8a/b2a no.a0744-4/29 ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) canceled by system reset or occurrence of interrupt. ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the cf, rc, and crystal oscillato rs automatically stop operation. 2) there are three ways of resetting the hold mode. (1) setting the reset pin to the lower level (2) setting at least one of the int0, int1, int2, int4, and int5 pins to the specified level (3) having an interrupt source established at port 0 ? x'tal hold mode: suspends instruction execution and the oper ation of the peripheral circuits except the base timer. 1) the cf and rc oscillators automatically stop operation. 2) the state of crystal oscillation established when the hold mode is entered is retained. 3) there are four ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level. (2) setting at least one of the int0, int1, int2, int4, and int5 pins to the specified level. (3) having an interrupt source established at port 0. (4) having an interrupt source established in the base timer circuit. ? package form ? qip100e(14 20): ?lead-free type? ? tqfp100(14 14): ?lead-free type? ? development tools ? evaluation (eva) chip : lc87ev690 ? emulator : eva62s + ecb876600d + sub875c00 + pod100qfp or pod100sqfp type b : ice-b877300 + sub875c00 + pod100qfp or pod100sqfp type b ? flash version : lc87f5cc8a
lc875cc8a/b2a no.a0744-5/29 package dimensions unit : mm (typ) 3151a package dimensions unit : mm (typ) 3274 sanyo : qip100e(14x20) 20.0 23.2 14.0 17.2 0.15 0.8 (2.7) 3.0max 0.1 0.3 0.65 (0.58) 130 80 51 31 50 100 81 sanyo : tqfp100(14x14) 100 125 26 50 51 75 76 14.0 (1.0) (1.0) 0.1 0.125 16.0 0.2 0.5 1.2max 0.5 14.0 16.0
lc875cc8a/b2a no.a0744-6/29 pin assignments sanyo: qip100e(14 20) ?lead-free type? pb6 pb5 pb4 pb3 pb2 pb1 pb0 v ss 3 v dd 3 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pa0 pa1 pa2 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 pb7 p36 p35/urx2 p34/utx2 p33/urx1 p32/utx1 p31/pwm5 p30/pwm4 p27/int5/t1in/t0lcp/t0hcp p26/int5/t1in/t0lcp/t0hcp p25/int5/t1in/t0lcp/t0hcp p24/int5/t1in/t0lcp/t0hcp/int7/t0hcp1 p23/int4/t1in/t0lcp/t0hcp p22/int4/t1in/t0lcp/t0hcp p21/int4/t1in/t0lcp/t0hcp p20/int4/t1in/t0lcp/t0hcp/int6/t0lcp1 p07/t7o p06/t6o p05/cko p04 p03 p02 p01 p00 v ss 2 v dd 2 pwm0 pwm1 si2p3/sck20 si2p2/sck2 pa3/an12 pa4/an13 pa5/an14 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in/t0lcp p73/int3/t0in/t0hcp res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz si2p1/si2/sb2 si2p0/so2 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 v dd 4 v ss 4 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 lc875cc8a LC875CB2A top view
lc875cc8a/b2a no.a0744-7/29 sanyo: tqip100(14 14) ?lead-free type? p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in/t0lcp p73/int3/t0in/t0hcp res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 pwm1 si2p3/sck20 si2p2/sck2 si2p1/si2/sb2 si2p0/so2 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 v dd 4 v ss 4 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 p17/t1pwmh/buz p16/t1pwml 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 p36 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 v ss 3 v dd 3 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pa0 pa1 pa2 pa3/an12 pa4/an13 pa5/an14 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p35/urx1 p34/utx2 p33/urx1 p32/utx1 p31/pwm5 p30/pwm4 p27/int5/t1in/ t0lcp/t0hcp p26/int5/t1in/ t0lcp/t0hcp p25/int5/t1in/ t0lcp/t0hcp p24/int5/t1in/ t0lcp/t0hcp/int7/t0hcp1 p23/int4/t1in/ t0lcp/t0hcp p22/int4/t1in/ t0lcp/t0hcp p21/int4/t1in/ t0lcp/t0hcp p20/int4/t1in/ t0lcp/t0hcp/int6/t0lcp1 p07/t7o p06/t6o p05/cko p04 p03 p02 p01 p00 v ss 2 v dd 2 pwm0 top view lc875cc8a LC875CB2A 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
lc875cc8a/b2a no.a0744-8/29 qip name tqfp qip name tqfp 1 pa3/an12 98 51 si2p2/sck2 48 2 pa4/an13 99 52 si2p3/sck20 49 3 pa5/an14 100 53 pwm1 50 4 p70/int0/t0lcp/an8 1 54 pwm0 51 5 p71/int1/t0hcp/an9 2 55 v dd 2 52 6 p72/int2/t0in/t0lcp 3 56 v ss 2 53 7 p73/int3/t0in/t0hcp 4 57 p00 54 8 res 5 58 p01 55 9 xt1/an10 6 59 p02 56 10 xt2/an11 7 60 p03 57 11 v ss 1 8 61 p04 58 12 cf1 9 62 p05/cko 59 13 cf2 10 63 p06/t6o 60 14 v dd 1 11 64 p07/t7o 61 15 p80/an0 12 65 p20/int4/t1in/t0lcp/t0hcp/ int6/t0lcp1 62 16 p81/an1 13 66 p21/int4/t1in/t0lcp/t0hcp 63 17 p82/an2 14 67 p22/int4/t1in/t0lcp/t0hcp 64 18 p83/an3 15 68 p23/int4/t1in/t0lcp/t0hcp 65 19 p84/an4 16 69 p24/int5/t1in/t0lcp/t0hcp/ int7/t0hcp1 66 20 p85/an5 17 70 p25/int5/t1in/t0lcp/t0hcp 67 21 p86/an6 18 71 p26/int5/t1in/t0lcp/t0hcp 68 22 p87/an7 19 72 p27/int5/t1in/t0lcp/t0hcp 69 23 p10/so0 20 73 p30/pwm4 70 24 p11/si0/sb0 21 74 p31/pwm5 71 25 p12/sck0 22 75 p32/utx1 72 26 p13/so1 23 76 p33/urx1 73 27 p14/si1/sb1 24 77 p34/utx2 74 28 p15/sck1 25 78 p35/urx2 75 29 p16/t1pwml 26 79 p36 76 30 p17/t1pwmh/buz 27 80 pb7 77 31 pe0 28 81 pb6 78 32 pe1 29 82 pb5 79 33 pe2 30 83 pb4 80 34 pe3 31 84 pb3 81 35 pe4 32 85 pb2 82 36 pe5 33 86 pb1 83 37 pe6 34 87 pb0 84 38 pe7 35 88 v ss 3 85 39 v ss 4 36 89 v dd 3 86 40 v dd 4 37 90 pc7 87 41 pf0 38 91 pc6 88 42 pf1 39 92 pc5 89 43 pf2 40 93 pc4 90 44 pf3 41 94 pc3 91 45 pf4 42 95 pc2 92 46 pf5 43 96 pc1 93 47 pf6 44 97 pc0 94 48 pf7 45 98 pa0 95 49 si2p0/so2 46 99 pa1 96 50 si2p1/si2/sb2 47 100 pa2 97
lc875cc8a/b2a no.a0744-9/29 system block diagram interru p t control cf standb y control rc x?tal clock generator ir pla rom pc sio0 sio1 timer 0 timer 1 bus interface port 1 port 0 port 7 port 8 adc port 2 int4, 5, 6, 7 acc b register c register psw rar ram stack pointer watchdog timer pwm0 pwm1 base time r alu int0 to 3 noise rejection filte r sio2 timer 4 timer 5 port 3 timer 6 timer 7 port e port c mrc port a port b port f pwm4 uart1 uart2 pwm5
lc875cc8a/b2a no.a0744-10/29 pin description pin name i/o function description option v ss 1, v ss 2 v ss 3, v ss 4 - power supply pin (-) no v dd 1, v dd 2 v dd 3, v dd 4 - power supply pin (+) no port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 4-bit units ? pull-up resistor can be turned on and off in 4-bit units ? hold release input ? port 0 interrupt input ? pin functions p05: system clock output p06: timer 6 toggle output p07: timer 7 toggle output yes port 1 p10 to p17 i/o ?8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? pin functions p10: sio0 data output p11: sio0 data input, bus i/o p12: sio0 clock i/o p13: sio1 data output p14: sio1 data input, bus i/o p15: sio1 clock i/o p16: timer 1 pwml output p17: timer 1 pwmh output, beeper output yes port 2 ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? pin functions p20: int4 input/hold reset input/timer 1 event input/timer 0l capture input/ timer 0h capture input/int6 input/timer 0l capture 1 input p21 to p23: int4 input/hold reset input/ timer 1 event input/timer 0l capture input/ timer 0h capture input p24: int5 input/hold reset input/timer 1 event input/timer 0l capture input/ timer 0h capture input int7 input/timer 0h capture 1 input p25 to p27: int5 input/hold reset input/ timer 1 event input/timer 0l capture input/ timer 0h capture input ? interrupt acknowledge type rising falling rising/ falling h level l level int4 int5 int6 int7 enable enable enable enable enable enable enable enable enable enable enable enable disable disable disable disable disable disable disable disable p20 to p27 i/o yes port 3 p30 to p36 i/o ? 7-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? pin functions p30: pwm4 output p31: pwm5 output p32: uart1 transmit p33: uart1 receive p34: uart2 transmit p35: uart2 receive yes continued on next page.
lc875cc8a/b2a no.a0744-11/29 continued from preceding page. pin name i/o function description option port 7 ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? other functions p70: int0 input/hold release input/timer 0l capture input/output for watchdog timer p71: int1 input/hold release input/timer 0h capture input p72: int2 input/hold release input/timer 0 event input/timer 0l capture input p73: int3 input with noise filter/time r 0 event input/timer 0h capture input ? interrupt acknowledge type rising falling rising/ falling h level l level int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable p70 to p73 i/o ? ad converter input port: an8 (p70), an9 (p71) no port 8 p80 to p87 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? other functions p80 to p87: ad converter input port no port a pa0 to pa5 i/o ? 6-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? shared functions pa3 to pa5: ad converter input port yes port b pb0 to pb7 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units yes port c pc0 to pc7 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units yes port e pe0 to pe7 i/o ? 8-bit i/o port ? i/o specifiable in 2-bit units ? pull-up resistor can be turned on and off in 1-bit units no port f pf0 to pf7 i/o ? 8-bit i/o port ? i/o specifiable in 2-bit units ? pull-up resistor can be turned on and off in 1-bit units no sio2 port si2p0 to si2p3 i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units ? shared functions: si2p0: sio2 data output si2p1: sio2 data input, bus i/o si2p2: sio2 clock i/o si2p3: sio2 clock output no pwm0 i/o ? pwm0 output port ? general-purpose i/o available no pwm1 i/o ? pwm1 output port ? general-purpose i/o available no res i reset pin no xt1 i ? input terminal for 32.768khz x'tal oscillation ? shared functions: an10: ad converter input port general-purpose input port must be connected to vdd1 if not to be used. no xt2 i/o ? output terminal for 32.768khz x'tal oscillation ? shared functions: an11: ad converter input port general-purpose i/o port must be set for oscillation and kept open if not to be used. no cf1 i ceramic resonator input pin no cf2 o ceramic resonator output pin no
lc875cc8a/b2a no.a0744-12/29 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name options selected in units of option ttype output type pull-up resistor 1 cmos programmable (note 1) p00 to p07 1 bit 2 n-channel open drain no 1 cmos programmable p10 to p17 p20 to p27 p30 to p36 1 bit 2 n-channel open drain programmable 1 cmos programmable pa0 to pa5 pb0 to pb7 pc0 to pc7 1 bit 2 n-channel open drain programmable pe0 to pe7 pf0 to pf7 - no cmos programmable p70 - no n-channel open drain programmable p71 to p73 - no cmos programmable p80 to p87 - no n-channel open drain no si2p0, si2p2 si2p3 pwm0, pwm1 - no cmos no si2p1 - no cmos (when selected as ordinary port) n-channel open drain (when sio2 data is selected) no xt1 - no input only no xt2 - no output for 32.768khz quartz oscillator n-channel open drain (when in general-purpose output mode) no note 1: programmable pull-up resistors for port 0 are controlled in 4-bit units (p00 to p03, p04 to p07).
lc875cc8a/b2a no.a0744-13/29 *1: make the following connection to minimize the noise input to the vdd1 pin and prolong the backup time. be sure to electrically short the vss1, vss2, vss3, and vss4 pins. (example 1) when backup is active in the hold mode, the high level of the port outputs is supplied by the backup capacitors. (example 2) the high-level output at the ports is unstable when the hold m ode backup is in effect. v ss 1 v ss 2 v ss 3 v ss 4 v dd 1 v dd 2 v dd 3 power supply back-up capacitor v dd 4 lsi lsi v ss 1 v ss 2 v ss 3 v ss 4 v dd 1 v dd 2 v dd 3 power supply back-up capacitor v dd 4
lc875cc8a/b2a no.a0744-14/29 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol pins /remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3, v dd 4 v dd 1=v dd 2=v dd 3=v dd 4 -0.3 +6.5 input voltage v i (1) xt1, cf1 -0.3 v dd +0.3 input/output voltage v io (1) ports 0, 1, 2 ports 3, 7, 8 ports a, b, c, e, f si2p0 to si2p3 pwm0, pwm1, xt2 -0.3 v dd +0.3 v ioph(1) ports 0, 1, 2, 3 ports a, b, c, e, f si2p0 to si2p3 cmos output select per 1 application pin -10 ioph(2) pwm0, pwm1 per 1 application pin. -20 peak output current ioph(3) p71 to p73 per 1 application pin. -5 iom(1) ports 0, 1, 2, 3 ports a, b, c, e, f si2p0 to si2p3 cmos output select per 1 application pin -7.5 iom(2) pwm0, pwm1 per 1 application pin. -15 average output current (note 1-1) iom(3) p71 to p73 per 1 application pin. -3 ioah(1) p71 to p73 total of all applicable pins -10 ioah(2) pwm0, pwm1 si2p0 to si2p3 total of all applicable pins -25 ioah(3) port 0 total of all applicable pins -25 ioah(4) port 0 pwm0, pwm1 si2p0 to si2p3 total of all applicable pins -45 ioah(5) ports 2, 3, b total of all applicable pins -25 ioah(6) ports a, c total of all applicable pins -25 ioah(7) ports 2, 3, a, b, c total of all applicable pins -45 ioah(8) ports f total of all applicable pins -25 ioah(9) ports 1, e total of all applicable pins -25 high level output current total output current ioah(10) ports 1, e, f total of all applicable pins -45 ma note 1-1: average output current is av erage of current in 100ms interval. continued on next page.
lc875cc8a/b2a no.a0744-15/29 continued from preceding page. specification parameter symbol pins/remarks conditions v dd [v] min typ max unit iopl(1) p02 to p07 ports 1, 2, 3 ports a, b, c, e, f si2p0 to si2p3 pwm0, pwm1 per 1 application pin. 20 iopl(2) p00, p01 per 1 application pin. 30 peak output current iopl(3) ports 7, 8, xt2 per 1 application pin. 10 ioml(1) p02 to p07 ports 1, 2, 3 ports a, b, c, e, f si2p0 to si2p3 pwm0, pwm1 per 1 application pin. 15 ioml(2) p00, p01 per 1 application pin. 20 average output current (note 1-1) ioml(3) ports 7, 8, xt2 per 1 application pin. 7.5 ioal(1) port 7, xt2 total of all applicable pins 15 ioal(2) port 8 total of all applicable pins 15 ioal(3) ports 7, 8, xt2 total of all applicable pins 20 ioal(4) pwm0, pwm1 si2p0 to si2p3 total of all applicable pins 45 ioal(5) port 0 total of all applicable pins 45 ioal(6) port 0 pwm0, pwm1 si2p0 to si2p3 total of all applicable pins 80 ioal(7) ports 2, 3, b total of all applicable pins 45 ioal(8) ports a, c total of all applicable pins 45 ioal(9) ports 2, 3, a, b, c total of all applicable pins 80 ioal(10) port f total of all applicable pins 45 ioal(11) ports 1, e total of all applicable pins 45 low level output current total output current ioal(12) ports 1, e, f total of all applicable pins 80 ma qip100e(14 20) 444 maximum power dissipation pd max tqfp100(14 14) ta=-30 to +70 c 345 mw operating ambient temperature topr -30 70 storage ambient temperature tstg -55 125 c note 1-1: average output current is av erage of current in 100ms interval.
lc875cc8a/b2a no.a0744-16/29 allowable operating conditions at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = v ss4 = 0v specification parameter symbol pins /remarks conditions v dd [v] min typ max unit 0.245 s tcyc 200 s 2.8 5.5 0.367 s tcyc 200 s 2.5 5.5 operating supply voltage v dd (1) v dd 1=v dd 2 =v dd 3=v dd 4 1.47 s tcyc 200 s 2.2 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2 =v dd 3=v dd 4 ram and register contents in hold mode. 2.0 5.5 v ih (1) ports 1, 2, 3 si2p0 to si2p3 p71 to p73 p70 port input / interrupt side 2.2 to 5.5 0.3v dd +0.7 v dd v ih (2) ports 0, 8 ports a, b, c, e, f pwm0, pwm1 2.2 to 5.5 0.3v dd +0.7 v dd v ih (3) p70 watchdog timer side 2.2 to 5.5 0.9v dd v dd high level input voltage v ih (4) xt1, xt2, cf1, res 2.2 to 5.5 0.75v dd v dd v il (1) 4.0 to 5.5 v ss 0.1v dd +0.4 v il (2) ports 1, 2, 3 si2p0 to si2p3 p71 to p73 p70 port input/ interrupt side 2.2 to 4.0 v ss 0.2v dd v il (3) 4.0 to 5.5 v ss 0.15v dd +0.4 v il (4) ports 0, 8 ports a, b, c, e, f pwm0, pwm1 2.2 to 4.0 v ss 0.2v dd v il (5) port 70 watchdog timer side 2.2 to 5.5 v ss 0.8v dd -1.0 low level input voltage v il (6) xt1, xt2, cf1, res 2.2 to 5.5 v ss 0.25v dd v 2.8 to 5.5 0.245 200 2.5 to 5.5 0.367 200 instruction cycle time (note 2-1) tcyc 2.2 to 5.5 1.470 200 s 2.8 to 5.5 0.1 12 2.5 to 5.5 0.1 8 ? cf2 pin open ? system clock frequency division rate=1/1 ? external system clock duty =505% 2.2 to 5.5 0.1 2 2.8 to 5.5 0.2 24.4 2.5 to 5.5 0.2 16 external system clock frequency fexcf(1) cf1 ? cf2 pin open ? system clock frequency division rate=1/2 2.2 to 5.5 0.2 4 fmcf(1) cf1, cf2 12mhz ceramic oscillation see fig. 1. 2.8 to 5.5 12 fmcf(2) cf1, cf2 8mhz ceramic oscillation see fig. 1. 2.5 to 5.5 8 fmcf(3) cf1, cf2 4mhz ceramic oscillation see fig. 1. 2.2 to 5.5 4 fmrc internal rc oscillation 2.2 to 5.5 0.3 1.0 2.0 fmmrc frequency variable rc oscillation source oscillation 2.2 to 5.5 16 mhz oscillation frequency range (note 2-2) fsx?tal xt1, xt2 32.768khz crystal oscillation. see fig. 2. 2.2 to 5.5 32.768 khz note 2-1: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-2: see tables 1 and 2 for the oscillation constants.
lc875cc8a/b2a no.a0744-17/29 electrical characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol pins /remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 2 ports 3, 7, 8 ports a, b, c,e,f si2p0 to si2p3 res pwm0, pwm1 output disable pull-up resistor off v in =v dd (including the off-leak current of the output tr.) 2.2 to 5.5 1 i ih (2) xt1, xt2 using as an input port v in =v dd 2.2 to 5.5 1 high level input current i ih (3) cf1 v in =v dd 2.2 to 5.5 15 i il (1) ports 0, 1, 2 ports 3, 7, 8 ports a, b, c, e, f si2p0 to si2p3 res pwm0, pwm1 output disable pull-up resistor off v in =v ss (including the off-leak current of the output tr.) 2.2 to 5.5 -1 i il (2) xt1, xt2 using as an input port v in =v ss 2.2 to 5.5 -1 low level input current i il (3) cf1 v in =v ss 2.2 to 5.5 -15 a v oh (1) i oh =-1.0ma 4.5 to 5.5 v dd -1 v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) ports 0, 1, 2, 3 ports a, b, c, e, f si2p0 to si2p3 i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v oh (4) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (5) ports 71, 72, 73 i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v oh (6) i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (7) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 high level output voltage v oh (8) pwm0, pwm1 p30, p31 (pwm4, 5 output mode) i oh =-1.0ma 2.2 to 5.5 v dd -0.4 v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.6ma 3.0 to 5.5 0.4 v ol (3) ports 0, 1, 2, 3 ports a, b, c, e, f si2p0 to si2p3 pwm0, pwm1 i ol =1.0ma 2.2 to 5.5 0.4 v ol (4) i ol =30ma 4.5 to 5.5 1.5 v ol (5) i ol =5.0ma 3.0 to 5.5 0.4 v ol (6) p00, p01 i ol =2.5ma 2.2 to 5.5 0.4 v ol (7) i ol =1.6ma 3.0 to 5.5 0.4 low level output voltage v ol (8) ports 7, 8, xt2 i ol =1.0ma 2.2 to 5.5 0.4 v rpu(1) 4.5 to 5.5 15 35 80 pull-up resistation rpu(2) ports 0, 1, 2, 3 port 7 ports a, b, c, e, f v oh =0.9v dd 2.2 to 5.5 15 35 150 k hysteresis voltage vhys res ports 1, 2, 7 si2p0 to si2p3 2.2 to 5.5 0.1v dd v pin capacitance cp all pins ? for pins other than that under test: v in =v ss ? f=1mhz ? ta=25 c 2.2 to 5.5 10 pf
lc875cc8a/b2a no.a0744-18/29 serial i/o characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) ? see fig. 6. 1 tsckha(1a) ? continuous data transmission/ reception mode ? sio2 is not in use simultaneous. ? see fig. 6. ? (note 4-1-2) 4 input clock high level pulse width tsckha(1b) sck0(p12) ? continuous data transmission/ reception mode ? sio2 is in use simultaneous. ? see fig. 6. ? (note 4-1-2) 2.2 to 5.5 6 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected. ? see fig. 6. 1/2 tsck tsckha(2a) ? continuous data transmission/ reception mode ? sio2 is not in use simultaneous. ? cmos output selected. ? see fig. 6. tsckh(2) +2tcyc tsckh(2) +(10/3)tcyc serial clock output clock high level pulse width tsckha(2b) sck0(p12) ? continuous data transmission/ reception mode ? sio2 is in use simultaneous. ? cmos output selected. ? see fig. 6. 2.2 to 5.5 tsckh(2) +2tcyc tsckh(2) +(16/3)tcyc tcyc data setup time tsdi(1) 0.03 serial input data hold time thdi(1) si0(p11), sb0(p11) ? must be specified with respect to rising edge of sioclk ? see fig. 6. 2.2 to 5.5 0.03 tdd0(1) ? continuous data transmission/ reception mode ? (note 4-1-3) (1/3)tcyc +0.05 input clock tdd0(2) ? synchronous 8-bit mode. ? (note 4-1-3) 1tcyc +0.05 serial output output clock output delay time tdd0(3) so0(p10), sb0(p11), ? (note 4-1-3) 2.2 to 5.5 (1/3)tcyc +0.05 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 6.
lc875cc8a/b2a no.a0744-19/29 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) ? see fig. 6. 2.2 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? cmos output selected. ? see fig. 6. 2.2 to 5.5 1/2 tsck data setup time tsdi(2) 0.03 serial input data hold time thdi(2) si1(p14), sb1(p14) ? must be specified with respect to rising edge of sioclk ? see fig. 6. 2.2 to 5.5 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 6. 2.2 to 5.5 (1/3)tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use.
lc875cc8a/b2a no.a0744-20/29 3. sio2 serial i/o characteristics (note 4-3-1) specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit frequency tsck(5) 2 low level pulse width tsckl(5) 1 tsckh(5) ? see fig. 6. 1 tsckha(5a) ? continuous data transmission/ reception mode of sio0 is not in use simultaneous. ? see fig. 6. ? (note 4-3-2) 4 input clock high level pulse width tsckha(5b) sck2 (si2p2) ? continuous data transmission/ reception mode of sio0 is in use simultaneous. ? see fig. 6. ? (note 4-3-2) 2.2 to 5.5 7 frequency tsck(6) 4/3 tcyc low level pulse width tsckl(6) 1/2 tsckh(6) ? cmos output selected. ? see fig. 6. 1/2 tsck tsckha(6a) ? continuous data transmission/ reception mode of sio0 is not in use simultaneous. ? cmos output selected. ? see fig. 6. tsckh(6) +(5/3)tcyc tsckh(6) + (10/3)tcyc serial clock output clock high level pulse width tsckha(6b) sck2 (si2p2), sck2o (si2p3) ? continuous data transmission/ reception mode of sio0 is in use simultaneous. ? cmos output selected. ? see fig. 6. 2.2 to 5.5 tsckh(6) +(5/3)tcyc tsckh(6) + (19/3)tcyc tcyc data setup time tsdi(3) 0.03 serial input data hold time thdi(3) si2(si2p1), sb2(si2p1) ? must be specified with respect to rising edge of sioclk ? see fig. 6. 2.2 to 5.5 0.03 serial output output delay time tdd0(5) so2(si2p0), sb2(si2p1) ? must be specified with respect to falling edge of sioclk ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 6. 2.2 to 5.5 (1/3)tcyc +0.05 s note 4-3-1: these specifications are theoretical values. add margin depending on its use. note 4-3-2: to use serial-clock-input , a time from si2run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha.
lc875cc8a/b2a no.a0744-21/29 pulse input conditions at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol pins /remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72) int4(p20 to p23), int5(p24 to p27), int6(p20), int7(p24) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.2 to 5.5 1 tpih(2) tpil(2) int3(p73) (the noise rejection clock is selected to 1/32.) ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 2 tpih(3) tpil(3) int3(p73) (the noise rejection clock is selected to 1/32.) ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 64 tpih(4) tpil(4) int3(p73) (the noise rejection clock is selected to 1/128.) ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 256 tcyc high/low level pulse width tpil(5) res reset acceptable 2.2 to 5.5 200 s ad converter characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol pins /remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute precision et (note 6-1) 3.0 to 5.5 1.5 lsb 4.5 to 5.5 11.74 (tcyc= 0.367 s) 97.92 (tcyc= 3.06 s) ad conversion time=32 tcyc (when adcr2=0) (note 6-2) 3.0 to 5.5 31.36 (tcyc= 0.980 s) 97.92 (tcyc= 3.06 s) 4.5 to 5.5 15.68 (tcyc= 0.245 s) 97.92 (tcyc= 1.53 s) conversion time tcad ad conversion time=64 tcyc (when adcr2=1) (note 6-2) 3.0 to 5.5 31.36 (tcyc= 0.490 s) 97.92 (tcyc= 1.53 s) s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p80) to an7(p87), an8(p70), an9(p71), an10(xt1), an11(xt2), an12(pa3), an13(pa4), an14(pa5) vain=v ss 3.0 to 5.5 -1 a note 6-1: the quantization erro r (1/2 lsb) is excluded from the absolute accuracy value. note 6-2: the conversion time refers to the interval from th e time the instruction for starting the converter is issued till the complete digital value corresponding to the analog input value is loaded in the required register.
lc875cc8a/b2a no.a0744-22/29 consumption current characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit iddop(1) 4.5 to 5.5 9.6 14 iddop(2) ? fmcf=12mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 12mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 2.8 to 4.5 4.8 8.5 iddop(3) 4.5 to 5.5 6.2 10 iddop(4) ? fmcf=8mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 8mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 2.5 to 4.5 3.2 6.5 iddop(5) 4.5 to 5.5 2.5 3 iddop(6) ? fmcf=4mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 4mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio. 2.2 to 4.5 1.2 2.5 iddop(7) 4.5 to 5.5 0.7 2 iddop(8) ? fmcf=0hz(oscillation stopped) ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped ?1/2 frequency division ratio. 2.2 to 4.5 0.3 1.5 iddop(9) 4.5 to 5.5 1.25 3 iddop(10) ? fmcf=0hz(oscillation stopped) ? fmx'al=32.768khz by crystal oscillation mode. ? system clock set to 1mhz with frequency variable rc oscillation ? internal rc oscillation stopped ? 1/2 frequency division ratio. 2.2 to 4.5 0.75 2 ma iddop(11) 4.5 to 5.5 27 65 normal mode consumption current (note 7-1) iddop(12) v dd 1 =v dd 2 =v dd 3 =v dd 4 ? fmcf=0hz(oscillation stopped) ? fmx'al=32.768khz by crystal oscillation mode. ? system clock set to 32.768khz side. ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio. 2.2 to 4.5 12 45 a note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. continued on next page.
lc875cc8a/b2a no.a0744-23/29 continued from preceding page. specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit iddhalt(1) 4.5 to 5.5 3.3 6 iddhalt(2) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 12mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 2.8 to 5.5 1.6 3.5 iddhalt(3) 4.5 to 5.5 2.3 4.5 iddhalt(4) ? halt mode ? fmcf=8mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 8mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 2.5 to 5.5 0.98 2.5 iddhalt(5) 4.5 to 5.5 1.2 2.0 iddhalt(6) ? halt mode ? fmcf=4mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 4mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio. 2.2 to 4.5 0.6 1.5 iddhalt(7) 4.5 to 5.5 0.3 1 iddhalt(8) ? halt mode ? fmcf=0hz(oscillation stopped) ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped ?1/2 frequency division ratio. 2.2 to 4.5 0.14 0.5 iddhalt(9) 4.5 to 5.5 1.0 2.5 iddhalt(10) ? halt mode ? fmcf=0hz(oscillation stopped) ? fmx'al=32.768khz by crystal oscillation mode. ? system clock set to 1mhz with frequency variable rc oscillation ? internal rc oscillation stopped ? 1/2 frequency division ratio. 2.2 to 4.5 0.5 1.8 ma iddhalt(11) 4.5 to 5.5 17 55 halt mode consumption current (note 7-1) iddhalt(12) v dd 1 =v dd 2 =v dd 3 =v dd 4 ? halt mode ? fmcf=0hz(oscillation stopped) ? fmx'al=32.768khz by crystal oscillation mode. ? system clock set to 32.768khz side. ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio. 2.2 to 4.5 5 30 iddhold(1) 4.5 to 5.5 0.02 10 current drain during hold mode iddhold(2) ? hold mode ? cf1=v dd or open (external clock mode) 2.2 to 4.5 0.008 8 iddhold(3) 4.5 to 5.5 14 40 current drain during time- base clock hold mode iddhold(4) v dd 1 ? timer hold mode ? cf1=v dd or open(external clock mode) ? fmx'tal=32.768khz by crystal oscillation mode 2.2 to 4.5 3.2 2.5 a note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors.
lc875cc8a/b2a no.a0744-24/29 uart(full duplex) oper ating conditions at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol pins /remarks conditions v dd [v] min typ max unit clock rate ubr, ubr2 utx1(p32), rtx1(p33), utx2(p33), rtx2(p34) 2.2 to 5.5 16/3 8192/3 tcyc data length: 7,8,and 9 bits (lsb first) stop bits: 1 bit (2-bit in continuous data transmission) parity bits: non example of continuous 8-bit data transmission mode processing (first transmit data = 55h) example of continuous 8-bit da ta reception mode processing (first receive data = 55h) start bit stop bit transmit data (lsb first) start of transmission end of transmission ubr, ubr2 stop bit received data (lsb first) ubr, ubr2 start of reception start bit end of reception
lc875cc8a/b2a no.a0744-25/29 v dd 1, v ss 1 terminal condition it is necessary to place capacitors between v dd 1 and v ss 1 as described below. ? place capacitors as close to v dd 1 and v ss 1 as possible. ? place capacitors so that the length of each terminal to th e each leg of the capacitor be equal (l1 = l1?, l2 = l2?). ? place high capacitance capacitor c1 and lo w capacitance capacitor c2 in parallel. ? capacitance of c2 must be more than 0.1 f. ? use thicker pattern for v dd 1 and v ss 1. v dd 3, v ss 3 terminal condition it is necessary to place capacitors between v dd 3 and v ss 3 as described below. ? place capacitors as close to v dd 3 and v ss 3 as possible. ? place capacitors so that the length of each terminal to the each leg of the capacitor be equal (l3 = l3?). ? capacitance of c3 must be more than 0.1 f. ? use thicker pattern for v dd 3 and v ss 3. v ss 1 v dd 1 l1? l2? l1 l2 c1 c2 v ss 3 v dd 3 l3? l3 c3
lc875cc8a/b2a no.a0744-26/29 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1. characteristics of a sample main system clock oscillator circuit with a ceramic oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c1 [pf] c2 [pf] rf1 [ ] rd1 [ ] operating voltage range [v] typ [ms] max [ms] remarks 12mhz cstce12m0g52-r0 (10) (10) open 470 2.8 to 5.5 0.05 0.15 internal c1, c2 cstce8m00g52-r0 (10) (10) open 2.2k 2.7 to 5.5 0.05 0.15 internal c1, c2 8mhz cstls8m00g53-b0 (15) (15) open 680 2.5 to 5.5 0.05 0.15 internal c1, c2 cstcr4m00g53-r0 (15) (15) open 3.3k 2.2 to 5.5 0.05 0.15 internal c1, c2 4mhz murata cstls4m00g53-r0 (15) (15) open 3.3k 2.2 to 5.5 0.05 0.15 internal c1, c2 the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after v dd goes above the operating voltage lower limit (see fig 4). characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a sanyo- designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2. characteristics of a sample subsystem clock oscillator circuit with a crystal oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c3 [pf] c4 [pf] rf2 [ ] rd2 [ ] operating voltage range [v] typ [s] max [s] remarks 32.768khz seiko epson mc-306 18 18 open 560k 2.2 to 5.5 1.3 3.0 applicatable cl value=12.5pf the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is ex ecuted and to the time interval that is required for the oscillation to get stabilized after the hold mode is reset (see fig 4). note: the components that are in volved in oscillation should be placed as close to the ic an d to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit figure 3 ac timing point c1 c2 cf cf2 cf1 c3 rd2 c4 x?tal xt2 xt1 rf2 rd1 rf1 0.5v dd
lc875cc8a/b2a no.a0744-27/29 reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization time v dd limit power supply res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unfixed reset instruction execution mode v dd gnd internal rc oscillation cf1, cf2 xt1, xt2 operation mode hold release signal hold release signal valid tmscf tmsx?tal hold halt
lc875cc8a/b2a no.a0744-28/29 figure 5 reset circuit figure 6 serial i/o waveforms figure 7 pulse input timing condition c res v dd r res res note : select c res and r res value to assure that at least 200s reset time is generated after the v dd becomes higher than the minimum operating voltage. tpil tpih data ram transmission period (only sio0,2) di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo data ram transmission period (only sio0,2)
lc875cc8a/b2a no.a0744-29/29 ps this catalog provides information as of january, 2007. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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